With the progress of a technology of a computer system or a telecommunication field, or the like, a demand for a low-cost, small-sized, and large-capacity semiconductor memory device used for storing information has been gradually increased. Further, since a demand for energy efficiency has also been increased, the technology development of the semiconductor memory device shows a tendency to suppress unnecessary current consumption.
Generally, a cell array storing data of a DRAM device has a structure that each of a plurality of cells configured of one NMOS transistor and one capacitor is connected to word lines and bit lines connected to each other in a net form.
An operation of a general DRAM device will be described briefly.
First, a /RAS signal, which is a main signal operating the DRAM device, is changed into an active state (low) and at the same time, an address signal input to a row address buffer is received. At this time, a row decoding operation selecting one of the word lines of the cell array by decoding the received row address signal is performed.
When the data of the cells connected to the selected word line are carried on a bit line pair BL, /BL configured of a bit line and a complementary bit line, a sense amplifier enable signal informing the operation timing of the sense amplifier is enabled to drive a bit line sense amplifier in a cell block selected by the row address. When the bit line sense amplifier is driven, the bit line pair BL, /BL maintaining predetermined potential difference ΔV by charge sharing is amplified at large potential difference. Thereafter, a column decoder selected by a column address turns-on a column transfer transistor transferring the data of the bit line to data bus lines to transfer the data transferred to the bit line pair BL, /BL to the data bus lines DB, DB/, which are then output to the outside of the device.
In the DRAM operation, the bit line sense amplifier should be driven after securing a sensing delay period shown in FIG. 1. In other words, the sense amplifier should be driven after securing sufficient potential difference ΔV between the bit line pair BL, /BL by the charge sharing, making it possible to prevent a phenomenon that the data of the bit line pair BL, /BL are reversed during the driving of the bit line sense amplifier.
Therefore, the bit line sense amplifier is controlled to be driven after securing sufficient potential difference ΔV between the bit line pair BL, /BL by controlling the enable start period of the sense amplifier enable signal using the delay circuit in the related art.
However, a core voltage VCORE level, which drives the delay circuit, rises when the external voltage VDD level is high or upon over driving so that the driving capability of the delay circuit is increased, thereby leading to a phenomenon that the delay period is short. When the delay period is short, the enable start period of the sense amplifier enable signal is early so that the sense amplifier is driven at a state where sufficient potential difference ΔV between the bit line pair BL, /BL is not secured, thereby leading to the phenomenon that the data of the bit line pair BL, /BL are reversed during the driving of the bit line sense amplifier.